Job Description

Standard Cell Layout Engineer: Location: Bangalore, India Experience: 3-5 Years Job type: Full time : Summary: We are seeking an experienced Standard Cell Layout Engineer to join our team in Bangalore. The ideal candidate will play a crucial role in the development and optimization of standard cell libraries for integrated circuit (IC) designs. This position demands a strong understanding of semiconductor design principles, layout tools, and an ability to work collaboratively with cross-functional teams. Key Responsibilities:

• Standard Cell Library Development: Collaborate with the design and architecture teams to define and develop standard cell libraries. Create, modify, and optimize standard cell layouts to meet performance, power, and area (PPA) targets. Ensure that standard cell designs adhere to industry standards and best practices.
• Layout Design: Utilize CAD tools and layout software to design, implement, and verify standard cell layouts. Optimize cell placements, routing, and spacing to achieve optimal PPA metrics. Perform physical verification checks (DRC, LVS, ERC) to ensure layout quality and compliance with design rules.
• Process and Technology Awareness: Stay up-to-date with semiconductor manufacturing processes and technologies. Adapt layout strategies to accommodate changes in process technology.
• Collaboration and Communication: Work closely with cross-functional teams, including design, verification, and manufacturing, to ensure successful tape-outs. Communicate progress, challenges, and solutions effectively with team members and stakeholders.
• Documentation: Maintain comprehensive documentation of standard cell layouts, design rules, and processes. Contribute to the development of layout guidelines and best practices.

Requirements:

• Bachelor\'s degree in Electrical Engineering or a related field. A Master\'s degree is a plus.
• 3-5 years of experience in standard cell layout design within the semiconductor industry.
• Proficiency in layout design tools and CAD software (e.g., Cadence Virtuoso, Synopsys ICC, Mentor Graphics Calibre).
• Strong understanding of semiconductor fabrication processes and CMOS technology.
• Knowledge of physical verification tools (DRC, LVS, ERC) and experience with debugging and resolving violations.
• Familiarity with scripting languages (e.g., Python, TCL) for automation tasks is advantageous.
• Excellent problem-solving skills, attention to detail, and the ability to work in a collaborative team environment.
• Effective communication skills in English, both written and verbal.

Job Type: Full-time Salary: 300,000.00 - 1,000,000.00 per year Schedule:

• Monday to Friday

Application Question(s):

• How many years of total work experience do you have?
• How many years of experience do you have as a Standard Cell Layout Engineer?
• What is your Expected CTC Per Annum (Please mention in Lakhs)?
• What is your current notice period (please mention in days)?
• What is your Current CTC Per Annum (Please mention in Lakhs)?
• Will you be able to reliably commute or relocate to Bengaluru for this job?

Work Location: In person