Job Description

Lattice OverviewThere is energy here\xe2\x80\xa6energy you can feel crackling at any of our international locations. It\xe2\x80\x99s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a \xe2\x80\x9cteam first\xe2\x80\x9d organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you\xe2\x80\x99re looking for.Lattice is seeking candidates for the position of Staff Software Development Engineer in FPGA place and route. This is a full-time position located in Pune, India.Responsibilities & SkillsSummary:The successful candidate will join a team designing and developing Lattice FPGA software tools. The candidate will contribute to delivering software solution for Lattice FPGA development with emphasis on static timing analysis (STA) tool. The candidate is expected to be an expert in static timing analysis with knowledge on how to optimize STA to achieve fast runtime and minimal memory utilization. The candidate will work with other software developers to improve STA engine performance and support new features. The responsibility also includes customer support and new FPGA product support. The candidate is expected to maintain existing software products and interact with other teams to facilitate a value-added solution too.Accountabilities:

• Develop new static timing analysis features.
• Support static timing analysis for new Lattice FPGA products.
• Improve static timing analysis QoR.
• Create unit tests to validate implementation and ensure high quality.

Qualifications:

• BS/MS/PhD in Electrical Engineering or Computer Science or Computer Engineering.
• Proficient with C/C++, data structure, graph algorithms, logic design and shell scripts.
• Strong background and experience in data structures and algorithms.
• Experience of static timing analysis development is a must.
• Experience of FPGA tool development is preferred.
• Strong written and verbal communication skills, and collaboration skill.
• Experience of multi-processing development is a plus.
• Solid understanding in FPGA architectures is a plus.
• 8+ years of experience in static timing analysis development.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.LatticeFeel the energy.

Lattice Semiconductor