Job Description

Lattice OverviewLattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products.The Company\'s broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice\xe2\x80\xa6and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what\xe2\x80\x99s next.Responsibilities & SkillsSystem and Software team mission is to create growth opportunities for Lattice by delivering solutions consisting of systems and software for diverse applications like AI/ML at edge. As a Sr. Design Engineer, you will be responsible to innovate, design and develop efficient techniques to inference neural networks on Lattice FPGA. Prior experience in developing ML inference engine or complex image processing IP is a must to have skill for this position.We are seeking a highly motivated Sr. design engineer to work in our neural network inference engine. The job involves design and development of techniques to address compute and memory bandwidth issues while inferencing neural network on a resource constrained device. Any prior knowledge of domain specific processor or accelerator design is a big plus. You are responsible for timing closure, power/area reduction of design implemented on FPGA.RequirementsKey Skills

• Prior experience in RTL design for domain specific processor.
• In depth understanding of AI/ML operations.
• Experience in timing closure on designs targeted for FPGA.
• TL development with Verilog-HDL.
• Good understanding of mapping ML operations to logic.
• Low power design techniques.
• RISC-V based system extension.

• BS/MS/PhD in Electronics or Computer Engineering minimum of 8 years (6 years for MS) of design experience.
• Independent and self-motivated, capable of executing under dynamic environment and uncertainties.
• Innovative, problem solver who likes to come up with newer and better solutions for existing problems.
• Good communication skill.

Lattice Semiconductor