Job Description

Job Details:: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.Qualifications: Minimum QualificationsGraduate of Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with at least 6+ years' experience in the following:Micro-architecture and RTL design for advanced SoCsExpertise in link and network layers of coherent fabric systemsHands-on experience in developing protocol bridges for interface translations; and experience with coherent protocols (CXL, CCIX, PCIe, or similar) and interconnect technologies OR;Graduate of Master's Degree in Electrical Engineering, Computer Engineering, or a related field with at least 4+ years' experience in the followingMicro-architecture and RTL design for advanced SoCsExpertise in link and network layers of coherent fabric systemsHands-on experience in developing protocol bridges for interface translations; and experience with coherent protocols (CXL, CCIX, PCIe, or similar) and interconnect technologies OR;PhD in Electrical Engineering, Computer Engineering, or a related field.Technical Experience- Proficiency in RTL design using Verilog or SystemVerilog.- Knowledge in micro-architecture and pipeline design.- Expertise in simulation, debugging, and performance tuning tools.- Knowledge in scripting languages (Python, Perl, or TCL) for automation and design flow optimization.Job Type: Experienced HireShift: Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intelxe2x80x99s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesxe2x80x94spanning software, processors, storage, I/O, and networking solutionsxe2x80x94that fuel cloud, communications, enterprise, and government data centers around the world.Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust N/AWork Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Intel