Job Description

Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM: Design architecture and circuit implementation, especially ultra high speed, ultra low power, or high density design portfolio. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation and full verification flow. Perform bit cell development and bit cell verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required Authority: Schedule own work flow Normally receives little instruction on day-to-day work, general instructions on new assignments. Demonstrates good judgment in selecting methods and techniques for obtaining solutions. Skills Requirements: Bachelors or Master s degree, Electrical Engineering, Telecommunication or related fields Proficient with CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction and knowledge of layout verification tools and debugging techniques. Programming capability- C-Shell, Perl. C++ or Java script a plus Excellent analytical and problem solving skills along with attention to details. Can develop a document, report or presentation for a range of tasks Microsoft Office: Word, Excel, PowerPoint, Shared point and Outlook Self-motivated, self-directed, detailed oriented and well organized Good analytical, problem solving and negotiation skills Ability to lead/mentor trainees and junior engineers as well as lead and manage projects. A strong command of English both verbal and written Strong interpersonal communication and team working skills Professionalism, Critical/Logical thinking, future goals focused High commitment to continuous learning

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