Job Description

The Allegro team is passionate about providing intelligent solutions that move the world toward a safer and more sustainable future. With more than 30 years of experience developing advanced semiconductor technology, innovation with purpose touches every aspect of our business. From customer engagement and employee recognition to technology advancement and serving the local communities in which we maintain offices, innovation consistently drives our mission and definition of success.
SUMMARY
The Product Validation Intern will contribute to the validation and characterization of Allegro MicroSystems' integrated circuits (ICs). This role offers practical experience in a fast-paced, innovative environment, working alongside experienced engineers. The intern will gain exposure to industry-standard test equipment and validation methodologies, developing valuable skills in semiconductor product testing and analysis.
RESPONSIBILITIES• Design Verification: Understand the product/design requirements Prepare Verification plan documents. Testbench development using UVM Develop testcases, assertions, functional coverage. Develop scripts for running simulations
• AMS Verification: Understand the product/Analog module requirements Prepare Verification plan documents for Analog modules. Develop testcases using Verilog AMS, Verilog-A, WREAL, SV-RNM
• Post Silicon Validation: Understand the product validation requirements Prepare Validation plan document and develop testcases using Python script. Execute the validation tests on silicon, debug the issue and report them to designer. Generate Validation reports based in the silicon results.


ESSENTIAL REQUIREMENTS• Pursuing B.Tech/M.Tech degree in ECE/EEE/VLSI/Embedded or equivalent branch
• Good Knowledge in Analog basics ( voltage dividers ,Op-Amp ,RC/RL filters, buffers etc.) and/or digital design basics (Counter designs, FF, memories etc)
• Strong analytical and programming/logical skills
• Knowledge in Verilog, SystemVerilog
• Hands on experience in Analog Mixed Signal verification simulation tools, Digital simulation tools (Questasim/Cadence/VCS)
• Knowledge in scripting like Perl/Python/Tcl/Tk
• Excellent communication and documentation skills


DESIRED QUALIFICATIONS• Knowledge in Universal Verification Methodology(UVM)
• Good Knowledge in Verilog AMS, Verilog-A, WREAL, SV-RNM
• Knowledge in assertions and functional coverage
• Experience in Lab Automation with Instruments like Oscilloscope, Source Meter, Bench multimeters, Thermo-stream, Logic Analyzer, Spectrum Analyzer, Power Supplies, Signal Generators etc.


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