Job Description

Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification, Take complete ownership for implementation of both Top/Block level designs. Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 28nm nodes or below. Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM, Timing Closure, constraint (sdc) development) Well versed with the block and chip level timing closure (STA) and timing closure methodologies. Also need to have experience with constraints development. Experience in Hierarchical and Flat timing flow bring-up and timing analysis on interface paths. Block level/Fullchip/SOC level/Mixed signal timing path analysis and fixing. Must have knowledge of low power design. (cpf, upf CLP). Should be able to provide clear directions to the team on various implementation and signoff flows Should be well versed in LEC flow and debugging issues independently. Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop Role involves analyzing DRC, LVS,ERC and PERC rule files for industry standard layout verification. Qualifications Must have minimum Bachelors degree in EE/ECE (degree s related to electronics) from a reputed institute. Must have at least 5 - 10 years of experience, out of which at least 5 years should be related to physical design at chip level / block level. Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus

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