Job Description

Job Requirements

Lead a PD team for a customer


Able to train engineers under him/her


Interact with customer

Work Experience

• 10+ years of professional experience in physical design, preferably with high performance designs.
• Experience in minimum one of the Full Chip Integration activities such as Full Chip Floor Planning, Power Planning , Bus Planning, Full Chip timing, Full Chip Reliability and Full Chip Physical Verification is desirable.
• Mentoring/leading a team of 6 to 8 PD Engineers is desirable.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm
• Excellent physical design and timing background.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.