Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.The Cadence Advantage
The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success.
Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day.JOB Summary:
We have an immediate opening in the Electrical Validation team at Cadence Design Systems Bangalore, for the post of "Lead Design Engineer".The responsibility primarily entails performing pre and post silicon Physical Layer Electrical Validation on Cadence's High Speed SERDES IP.
Activities include

• Designing the hardware and software infrastructure required to enable validation (Test PCBs, Controlling FPGA platforms, Labview/Python automation)
• Implementing test suites for rigorously testing the compliance of the IP to Physical Layer Electrical specifications
• Debugging Silicon issues and generating high quality test reports for customers

What we are looking for in potential candidates is listed below.Minimum Qualifications:
BE/BTECH/ME/MTECH Equivalent Degree

• 3-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
• Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO
• Hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzers, Bit Error Rate Testers (BERT)

Preferred Qualifications:

• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects
• 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping is a plus
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug
• Familiarity with RTL coding for FPGA, Labview, Python, C/C++, TCL

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Cadence Design Systems