Job Description

Minimum qualifications: Bachelor\'s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of full chip design verification experience. Experience verifying digital logic at RTL using SystemVerilog at Subsyste

Minimum qualifications: Bachelor\'s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 4-12 years of full chip design verification experience. Experience verifying digital logic at RTL using SystemVerilog at Subsystem and full chip level. Experience in debugging of full chip flows and test sequences, reusable testbench design, and development at SubSystem and full chip level. Preferred qualifications: Master\'s degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with performance, latency, concurrency, and use case verification at full chip level. Experience with full chip boot flow, clocking, and security verification. Experience with Low Power Verification, Power Flows, and GLS. Experience with Portable Stimulus standard based reusable test generation. About the job Our computational challenges are so big, complex and unique we can\'t just purchase off-the-shelf hardware, we\'ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google\'s services. As a Hardware Engineer, you design and build the systems that are the heart of the world\'s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors. As a Full Chip Design Verification Engineer, you will be part of a Research and Development team developing high performance hardware and software to enable Google\'s continuous innovations. You will focus on building verification components, constrained-random testing, end-to-end system testing, and verification closure. Google\'s mission is to organize the world\'s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people\'s lives better through technology. Responsibilities Verify complex digital design blocks integration at Subsystem and Full Chip Level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM/SystemVerilog or create complex multi-core based C tests using reusable C test libs. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

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