LOCATION : NOIDADesign for Test (DFT) engineering organization at Renesas Electronics works on groundbreaking methods & technologies for innovations in the area of DFT architecture, verification & post silicon bring up of state-of-the-art semiconductor chips like system on a chip (SOCs) built on the latest semiconductor technology nodes.Responsibilities:
You will lead the DFT team activities at your location to drive the DFT structures implementation on the complex SOCs, verify the DFT operations of the chips & support the silicon bring up team using the DFT vectors on the ATE machines. Your team will own the following activities.
1. MBIST insertion to the design.
2. Compressor based Scan chain insertion.
3. BSCAN structure insertion based on the IEEE 1149.1 & 1149.6 standards.
4. Logic BIST implementation for the Self-test capability
5. Analog BIST implementation for selected analog blocks like PLLs, ADC & DACs.
6. IOBist methods implementation for IO structures of the SOCs.You will lead your team to work with cross-functional teams like design, physical design, verification teams to deliver the DFT solutions to the SOCs in predefined schedule.Qualifications
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