Familiarity with SoC style DFT architectures including multi-clock domain and low power design practices.Knowledge of DFT including Scan, MBISTKnowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)Good experience Top-level clock/reset circuit designKnowledge on DFT simulations and debugging.Hands On experience in ATPG/SCAN/MBIST/JTAG implementation at chip & block level.Exp: 3 Years to 15 Yearsmail to: pavan.pv@proxelera.comLocation: Bangalore/Hyderabadhttps://proxelera.com/
Expertia AI Technologies
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