Design Engineer

Year    Noida, Uttar Pradesh, India

Job Description


Role Description We are seeking a Sr. Engineer/Lead Engineer in the DFT domain to join our team full-time in Bengaluru. The role is primarily on-site and requires experience in DFT architectures and methodologies. Responsibilities include but are not limited to analyzing and synthesizing DFT requirements, developing DFT architecture and testing methodologies, developing and verifying test patterns, and integrating and verifying the DFT logic. Role requires experience in Zero delay and timing-based simulations, coverage gap analysis, MBIST insertion and verification. Qualifications Bachelor\'s or Master\'s degree in Electrical Engineering or related fields Experience in DFT architectures and methodologies. Experience with DFT tools such as Mentor Graphics, Synopsys, Cadence, Good understanding of digital logic, Verilog, VHDL, and timing concepts Strong analytical and problem-solving skills Excellent written and verbal communication skills to interact with cross-functional teams and clients. Self-motivated and able to thrive in a fast-paced, collaborative work environment. Experience in physical design tools such as ICC2 or Innovus is a plus Experience with ATE and post-silicon debug is a plus. Location -Noida and Bangalore Exp 3-10 Year

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Job Detail

  • Job Id
    JD3247680
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    Noida, Uttar Pradesh, India
  • Education
    Not mentioned
  • Experience
    Year