Work extensively with physical design, RTL, circuit design, CAD team/vendors on the development of design analysis and optimization flows Engage with the CPU physical design team on flow adoption Develop internal tools for PPA optimization and design analysis Requirements Solid working knowledge and experience of industry synthesis, PnR, and STA tools Solid understanding of design challenges and PPA improvement for high performance and low power design Solid understanding of logic design, CMOS circuit, and electrical engineering fundaments Proficiency in programming and scripting (Python, TCL, Perl) with strong fundamentals in data structures and algorithms Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills Self starter and highly motivated Education and Experience PhD, Masters Degree or Bachelors Degree in EE, EECS or CE with more than five years of experience.
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