Job Description

Key Skills : Experience - 4.5+yrs Location - bangalore/Hyderabad/ahmedabad Notice period - Immediate - 90days IP/Subsystem/SOC verification experience. Expertise in HVL and HDL (System Verilog, Verilog). Advanced knowledge of HVL methodology (UVM). Solid verification skills in problem solving, constrained random testing, and debugging. Solid understanding of reusable verification framework. Knowledge on PCI Express/DDR/USB will be a huge plus . Experience with System Verilog Assertion (SVA). Experience writing scripts in languages such as Perl or Python a plus . Programming experience in C/C++ and assembly a plus . Experience defining coverage space and writing coverage model a plus . Experience with GLS and Low Power Verification is a plus . Should be a great teammate with excellent communication skills and the desire to take on diverse challenges. Experience with formal verification tool (Jasper Gold or others) is not required but will be a huge plus . Description : Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology. Create verification plan from specification and in coordination with architects. Generate directed and ingenuous constrained random tests. Create/analyse coverage model and enhance testbench/test to increase coverage. Build automated flows for block and chip level verification. Debug failures, manage bug tracking, and close coverage. Hold detailed verification reviews and set standard for coding quality. Work closely with team members to improve methodology and flow. Have a nice day ahead !!

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