Asic Digital Design, Staff Engineer
Year Noida, Uttar Pradesh, India
Job Description
and RequirementsWe are seeking a Digital Verification Engineer who will be involved for functional verification of High Speed interface IPs. A dynamic personality with eager to learn, drive Pre-silicon verification activities, good knowledge of digital design & HDL implementation.
- Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards
- IP/design blocks/Firmware Specification study and build/update verification plans as well as the test cases
- Build/update functional verification environments to execute the test plans
- Implement checkers, assertions, random test generators, high level transactional models and bus functional models (BFMs) as per the verification plan needs
- Performing simulation, random and direct stimulus development and coverage review
- Work closely with digital designers for debug and achieve the desired coverage
- B.Tech/M.Tech with 3+ years of relevant experience
- Understanding of functional verification flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System Verilog
- Experience with System Verilog Assertions, code and functional coverage implementation and review
- Scripting and automation using TCL/PERL/Python
- Excellent debug and diagnostic skills
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Job Detail
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Job IdJD3302676
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationNoida, Uttar Pradesh, India
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EducationNot mentioned
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ExperienceYear