and RequirementsAt Synopsys, we\'re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we\'re powering it all with the world\'s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We\'re the world\'s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance-eliminating months off their project schedules.ASIC Digital Design, Sr Staff EngineerThe candidate will be a key member of the Synopsys ARC Processor hardware team working on next-generation ARC processor Verification.Individual contributor will be responsible for Verification of RTL design of microprocessor IP. Work with multi-site core teams. Review and improve verification test suites.At minimum, a Bachelor\'s/Master\'s degree in engineering is required with 8+ years of digital design verification experience using UVM and System Verilog. Strong background in RISC architectures, AMBA (AHB, AXI) protocols are required. Working experience in RISC microprocessor IP design, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful.The successful candidate is expected to:
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