Responsibilities: Develop and implement hierarchical flow methodologies for complex ASIC designs Work closely with cross-functional teams including architects, RTL designers, physical designers and verification teams to ensure high quality and timely delivery of design products Analyze timing reports and work with design teams to resolve timing issues Optimize design for power, performance and area Perform floorplanning and place-and-route of top-level modules Participate in the development of new design methodologies and flows to improve design quality, efficiency and time-to-market Requirements: BS/MS in Electrical Engineering or related field Sound understanding of hierarchical design methodologies and experience in various top-level implementation flows Expertise in timing analysis, optimization and closure Experience in SoC floorplan and design planning Familiarity with industry standard EDA tools such as Synopsys, Cadence, and Mentor Graphics Good scripting skills in Tcl, Perl, Python or shell Sound problem-solving skills, excellent written and verbal communication skills, and ability to work in a team environment 5-8 years of relevant exp
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